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HI2302
Co o HS nd RSheet a -Free Data a nt m pl i
Pb
October 25, 2005
FN4105.2
8-Bit, 50MSPS, Video A/D Converter with Clamp Function
The HI2302 is an 8-bit CMOS A/D Converter for video with synchronizing clamp function. The adoption of two-step parallel method achieves low power consumption and a maximum conversion rate of 50MSPS. For pin compatible lower sample rate converters refer to HI1179 (35MSPS) or HI1176 (20MSPS) data sheets.
Features
* Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit 0.5 LSB (DNL) * Maximum Sampling Frequency . . . . . . . . . . . . . 50 MSPS * Low Power Consumption . . . . . . . . . . . . . . . . . . . .125mW (Reference Current Excluded) * Built-In Input Clamp Function (DC Restore) * Clamp ON/OFF Function * Internal Voltage Reference * Input CMOS/TTL Compatible
Ordering Information
PART NUMBER HI2302JCQ TEMP. RANGE (oC) -40 to 85 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S
* Three-State TTL Compatible Output * Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single or +5V/3.3V Dual * Direct Replacement for Sony CXD2302Q
Applications
* Video Digitizing * Wireless Receivers * LCD Projectors/Panels * Cable Modems * RGB Graphics Processing * Camcorders * Instrumentation
Pinout
HI2302 (MQFP) TOP VIEW
DVSS DVSS VREF CCP CLE OE NC VRBS
D0 D1 D2 D3 D4 D5 D6 D7
32 31 30 29 28 27 26 25 1 24 2 23 3 4 5 6 7 8 22 21 20 19 18 17 9 10 11 12 13 14 15 16
VRB AVSS AVSS VIN AVDD AVDD VRT VRTS
DVDD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2000, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
AVDD
TEST
TEST
CLK
CLP
NC
NC
HI2302 Functional Block Diagram
DVSS 28
OE 30 DVSS 31
REFERENCE SUPPLY
25 VRBS 24 VRB
D0 (LSB) 1 23 AVSS D1 2 LOWER DATA LATCH LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 22 AVSS 21 VIN D3 4 LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 20 AVDD 19 AVDD D5 6 UPPER DATA LATCH 18 VRT 17 VRTS
D2
3
D4
5
D6
7
UPPER ENCODER (4-BIT)
UPPER SAMPLING COMPARATOR (4-BIT)
D7 (MSB)
8 16 AVDD
DVDD 10 TEST (OPEN) 11 CLK 12 CLOCK GENERATOR
+ TEST (OPEN) 9 15 CLP 14 NC 13 NC 29 CLE 27 CCP 26 VREF
NC 32
D-FF
2
HI2302
Absolute Maximum Ratings TA = 25oC
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Reference Voltage (VRT, VRB) . . . . . . . . . . .VDD +0.5 to VSS -0.5V Input Voltage (Analog) (VIN) . . . . . . . . . . . . . VDD +0.5 to VSS -0.5V Input Voltage (Digital) (VI) . . . . . . . . . . . . . . .VDD +0.5 to VSS -0.5V Output Voltage (Digital) (VO) . . . . . . . . . . . . .VDD +0.5 to VSS -0.5V
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MQFP - Lead Tips Only)
Operating Conditions
Supply Voltage (AVDD , AVSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5.25V (DVDD , DVSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5V (DVSS-AVSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 100mV Reference Input Voltage (VRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 and Above V (VRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 and Below V Analog Input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . 1.7VP-P Above Clock Pulse Width (tPW1 , tPW0) . . . . . . . . . . . . . . . . . . . 10ns (Min) Ambient Temperature (TOPR) . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER ANALOG CHARACTERISTICS Maximum Conversion Rate Minimum Conversion Rate Input Bandwidth Full Scale
fC = 50 MSPS, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC SYMBOL TEST CONDITIONS AVDD = 4.75 to 5.25V, TA = 20 to 75oC, VIN = 0.5 to 2.5V, fIN = 1kHz Triangular Wave Envelope RIN = 33 End Point -1dB -3dB NOTES MIN TYP MAX UNITS
fC Max fC Min BW
50 -
65 60 100 0.3 +0.7 -50 40 3 1.5 0 20 20
0.5 0.5 1.5 -30 60 40 40
MSPS MSPS MHz MHz LSB LSB mV mV % Degrees ns mV mV
Differential Nonlinearity Error Integral Nonlinearity Error Offset Voltage
ED EL EOT EOB DG DP tSD EOC
Potential Difference to VRT Potential Difference to VRB NTSC 40 IRE Mod Ramp fC = 14.3 MSPS
Note 2
-70 20 -
Differential Gain Error Differential Phase Error Sampling Delay Clamp Offset Voltage
VIN = DC, CIN = 10F tPCW = 2.75s, fC = 14.3 MSPS, fCLP = 15.75kHz fIN = 100kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 10MHz fIN = 25MHz
VREF = 0.5V VREF = 2.5V
0 0
Signal-To-Noise Ratio
SNR
-
45 44 44 43 38 32 51 46 49 46 45 45
-
dB dB dB dB dB dB dB dB dB dB dB dB
Spurious Free Dynamic
SFDR
fIN = 100kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 10MHz fIN = 25MHz
3
HI2302
Electrical Specifications
PARAMETER DC CHARACTERISTICS Supply Current Analog Digital Reference Current Reference Resistance (VRT - VRB) Self-Bias Voltage fC = 50 MSPS, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Continued) SYMBOL TEST CONDITIONS NOTES MIN TYP MAX UNITS
fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC IAD + IDD IAD IDD IREF RREF VRB VRT - VRB CAI1 CAI2 CDIN Shorts VRTS and AVDD Shorts VRBS and AVSS VIN , VIN = 1.5V + 0.07VRMS VRTS , VRT , VRB , VRBS , VREF TEST, CLK, CLP, CLE, OE CCP D0 to D7, TEST AVDD = 4.75 to 5.25V, DVDD = 3 to 5.5V, TA = -20oC to 75oC VI = 0V to AVDD , TA = 20oC to 75oC CLK TEST, CLP, CLE OE NTSC Ramp, Wave Input, CLE = 0V DVDD = 5V DVDD = 3.3V 4.1 260 0.52 1.80 2.2 -240 -240 -40 4 2.4 -40 -40 25 23 2 5.4 370 0.56 1.92 15 36 33 3 7.7 480 0.60 2.04 11 11 11 11 0.8 240 40 240 -2 -1.2 40 40 mA mA mA mA V V pF pF pF pF pF V V A A A mA mA mA mA A A
Input Capacitance
Output Capacitance
CAO CDO VIH VIL IIH IIL
Digital Input Voltage
Digital Input Current
Digital Output Current
IOH IOL IOH IOL IOZH IOZL
OE = 0V, DVDD = 5V TA = 20oC to 75oC OE = 0V DVDD = 3.3V TA = -20oC to 75oC OE = 3V DVDD = 3 to 5.5V TA = -20oC to 75oC CL = 15pF OE = 0V
VOH = DVDD - 0.8V VOL = 0.4V VOH = DVDD - 0.8V VOL = 0.4V VOH = DVDD VOL = 0V
TIMING
fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC tPZH tPHL tPLH tPHL DVDD = 5V DVDD = 3.3V RL = 1k CL = 15pF OE = 3V0V DVDD = 5V DVDD = 3.3V RL = 1k, CL = 15pF OE = 3V0V DVDD = 5V DVDD = 3.3V Note 4 5.5 9.5 8.5 4.3 11.8 7.6 2.5 4.5 6.0 3.0 7.0 5.0 3.5 2.5 1.75 5.5 5.5 2.75 7.5 8.0 3.75 9.0 8.0 16.3 12.0 ns ns ns ns ns ns ns ns ns ns s
Output Data Delay
Three-State Output Enable Time
tPZH tPZL tPZH tPZL
Three-State Output Enable Time Clamp Pulse Width NOTES:
tPHZ , tPLZ tPZH , tPZL tCPW
fC = 14.3MHz, CIN = 10F for NTSC Wave
2. The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001". EOT is a potential difference between VRT and a potential point where the voltage rises equivalent to 1/2 LSB of the voltage when the output data changes from "11111111" to "11111110". 3. The voltage of up to (AVDD + 0.5V) can be input when DVDD = 3.3V. But the output pin voltage is less than the DVDD voltage. When the digital output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DVDD + 0.5V) voltage to the digital output. 4. The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing systems to equal the values for NTSC.
4
HI2302 Timing Diagrams
tPW1 CLOCK 1.3V tPW0
ANALOG INPUT
N
N+1 N-2
N+2 N-1
N+3 N
N+4 N+1
DATA OUTPUT
N-3
= ANALOG SIGNAL SAMPLING POINT
FIGURE 1A. TIMING CHART
tr 4ns
tf 4ns 90% 3V
CLOCK
1.3V 10% 0V
DATA OUTPUT
0.7 DVDD 0.3 DVDD
tPLH, tPHL
FIGURE 1B. TIMING CHART
tr = 4.5ns
tf = 4.5ns 90% 3V
OE INPUT
1.3V tPLZ 10% tPZL 0V VOH
OUTPUT 1 10% tPHZ 90% OUTPUT 2 tPZH
1.3V VOL (DVSS) VOH (DVDD) 1.3V VOL
FIGURE 1C. TIMING CHART
5
HI2302 Timing Diagrams
(Continued)
VI (1) VI (2) VI (3) VI (4)
ANALOG INPUT
EXTERNAL CLOCK
(1)
(2)
(3)
(4)
UPPER COMPARATORS BLOCK
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
UPPER DATA
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
RV (0)
RV (1)
RV (2)
RV (3)
LOWER COMPARATORS A BLOCK
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
LOWER DATA A
LD (-1)
LD (1)
LOWER COMPARATORS B BLOCK
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
LOWER DATA B
LD (-2)
LD (0)
LD (2)
DIGITAL OUTPUT
OUT (-2)
OUT (-1)
OUT (0)
OUT (1)
FIGURE 1D. TIMING CHART II
Pin Descriptions
PIN NO. 1 to 8 SYMBOL D0 to D7
DVDD
EQUIVALENT CIRCUIT
DESCRIPTION D0 (LSB) to D7 (MSB) Output.
DI
DVSS
6
HI2302 Pin Descriptions
PIN NO. 9 TEST
DVDD
(Continued) EQUIVALENT CIRCUIT DESCRIPTION Leave open for normal use.
SYMBOL
9
DVSS
10 11 15
DVDD TEST CLP
AVDD
Digital Power Supply +5V or +3.3V. Leave open for normal use. Pull-up resistor is built in. Input for the clamp pulse. Clamps the signal voltage during low interval. Pull-up resistor is built in. The clamp function is enabled when CLE = Low. The clamp function is off and the device functions as a normal A/D converter when CLE = High. Pull-up resistor is built in. Clock Input. Set to Low level when no clock is input.
11 15
29
CLE
29
AVSS
12
CLK
AVDD
12
AVSS
13, 14, 32 16, 19, 20 17 18 24 25
NC AVDD VRTS VRT VRB VRBS
17 18 RT RREF RB 24 25 AVDD
Analog Power Supply +5V. Generates approximately +2.5V when shorted with AVDD . Reference Voltage (Top). Reference Voltage (Bottom). Generates approximately +0.6V when shorted with AVSS .
AVSS
21
VIN
AVDD
Analog Input.
21
AVSS
7
HI2302 Pin Descriptions
PIN NO. 22, 23 26 AVSS VREF
AVDD
(Continued) EQUIVALENT CIRCUIT Analog Ground. Clamp Reference Voltage Input. Clamps so that the reference voltage and the input signal during clamp interval are equal. DESCRIPTION
SYMBOL
26
AVSS
27
CCP
AVDD
Integrates the clamp control voltage. The relationship between the changes in CCP voltage and in VIN voltage is positive phase.
27
AVSS
28, 31 30
DVSS OE
AVDD
Digital Ground. Data is output when OE = Low. Pins D0 to D7 are at high impedance when OE = High. Pull-down resistor is built in.
30
AVSS
Digital Output
The following table shows the relationship between analog input voltage and digital output code.
INPUT SIGNAL VOLTAGE VRT * * * * * * * * VRB DIGITAL OUTPUT CODE STEP 0 * * * 127 128 * * * 255 0 0 0 0 1 0 0 1 0 1 0 1 * * * 0 0 0 0 MSB 1 1 1 1 * * * 0 1 0 1 0 1 0 1 1 1 LSB 1 1
8
HI2302 Electrical Specifications Measurement Circuits
MEASUREMENT POINT DVDD
TO OUTPUT PIN CL
MEASUREMENT POINT
RL TO OUTPUT PIN
CL
RL
NOTE: CL includes capacitance of probes. FIGURE 2. OUTPUT DATA DELAY MEASUREMENT CIRCUIT
+V
FIGURE 3. THREE-STATE OUTPUT MEASUREMENT CIRCUIT
S2 S1: ON IF A < B S2: ON IF B > A S1
+
-
-V AB COMPARATOR A8 B8
VIN
DUT HI2302
8
. . .
A1 A0 "0" DVM CLK (50 MSPS)
. . .
8 BUFFER
B1 B0
"1" 8 000 . . . 00 TO 111 . . . 10
CONTROLLER
FIGURE 4. INTEGRAL NONLINEARITY ERROR/DIFFERENTIAL NONLINEARITY ERROR/OFFSET VOLTAGE TEST CIRCUIT
HI20201 8 HI2302 100 IAE 40 IRE MODULATION BURST 0 -40 fC SYNC 0.5V 620 TTL -5.2V ECL 2.5V ECL 620 -5.2V CLK TTL 8 10-BIT D/A VECTOR SCOPE
NTSC SIGNAL SOURCE
VIN
D.G. D.P.
S.G. (CW)
FIGURE 5. DIFFERENTIAL GAIN ERROR, DIFFERENTIAL PHASE ERROR TEST CIRCUIT
9
HI2302 Electrical Specifications Measurement Circuits
VDD VRT VIN VRB CLK OE GND VOL
(Continued)
2.5V 0.5V
IOL
2.5V 0.5V +
VDD VRT VIN VRB CLK OE GND VOH
IOH
-
+
-
FIGURE 6. DIGITAL OUTPUT CURRENT TEST CIRCUIT
Operation
(See Block diagram and Timing Chart II)
Notes On Operation
* VDD , VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1F set as close as possible to the pin to bypass to the respective GNDs. * Analog Input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However, it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be prevented by insetting a resistance of about 33 in series between the amplifier output and A/D input. When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect on the characteristics of A/D conversion. * Clock Input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. * Reference Input Voltage VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1F, stable characteristics are obtained. By shorting VDD and VRTS , VSS and VRBS respectively, the self-bias function that generates VRT = about 2.5V and VRB = about 0.6V, is activated. * Timing Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 9ns (DVDD = 5V). * OE Pin Pins 1 to 8 (D0 to D7) are in the output mode by leaving OE open or connecting it to DVSS , and they are in the high impedance mode by connecting it to DVDD .
* The HI2302 is a two-step parallel system A/D converter featuring a 4-bit upper comparator block and two lower comparator blocks of 4-bit each. The reference voltage that is equal to the voltage between VRT - VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. VRTS and VRBS pins serve for the self generation of VRT (reference voltage top) and VRB (reference voltage bottom), and they are also used as the sense pins as shown in the Application Circuit examples Figures 10 and 11. * This IC uses an offset cancel type comparator which operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the Timing Chart II with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. * The operation of respective parts is as indicated in the Timing Chart II. For instance, input voltage VI (1) is sampled with the falling edge of the external clock (1) by means of the upper comparator block and the lower comparator A block. The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2). Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator A Block finalizes comparison data LD (1) with the rising edge of the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
10
HI2302 Application Circuits
ACO4 CLOCK IN CLAMP PULSE IN 0.01 +5V (ANALOG) 17 18 19 VIDEO IN 20 10 + 0.1 10P 23 24 +5V (ANALOG) 0.01 VREF 20K GND (ANALOG) 0.01 GND (DIGITAL) 25 26 27 28 29 30 31 32 2 1 D1 D0 33 21 22 4 3 D3 D2 16 15 14 13 12 11 10 OPEN 9 8 7 6 5 D7 D6 D5 D4 +5V (DIGITAL) 0.1
FIGURE 7. SINGLE +5V POWER SUPPLY WHEN CLAMP IS USED (SELF-BIAS USED)
ACO4 CLOCK IN 16 0.01 +5V (ANALOG) 17 18 19 20 VIDEO IN 10 + 10p 0.1 33 21 22 23 24 0.01 25 26 27 28 29 30 31 32 DAC * PWM * ETC. INFORMATION OTHER THAN THAT FOR CLAMP INTERVAL IS AT HIGH IMPEDANCE 4 3 2 1 15 14 13 12 11 10 OPEN 9 8 7 6 5 SUBTRACTER * COMPARATOR * ETC. CLAMP LEVEL SETTING DATA +5V (DIGITAL) 0.1
GND (DIGITAL)
GND (ANALOG)
NOTES: 5. The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase. 6. VIN / VCCP = 3.0 (fS = 20 MSPS). FIGURE 8. SINGLE +5V POWER SUPPLY DIGITAL CLAMP (SELF-BIAS USED)
11
HI2302 Application Circuits
(Continued)
+5V (DIGITAL) ACO4 CLOCK IN 16 +5V (ANALOG) 0.01 17 18 19 VIDEO IN 33 21 0.1 10p 23 24 25 26 27 28 29 30 31 32 2 1 D1 D0 22 4 3 D3 D2 20 15 14 13 12 11 10 OPEN 9 8 7 6 5 D7 D6 D5 D4 0.1
0.01
GND (DIGITAL) GND (ANALOG)
FIGURE 9. SINGLE +5V POWER SUPPLY WHEN CLAMP IS NOT USED (SELF-BIAS USED)
+5V (DIGITAL) ACO4 0.1 CLOCK IN CLAMP PULSE IN + 0.01 +5V (ANALOG) 19 VIDEO IN 20 10 33 21 10p 0.01 24 VRB + +5V (ANALOG) VREF 20K 25 26 27 28 0.01 GND (DIGITAL) 29 30 31 32 1 D0 0.1 22 23 4 3 2 D3 D2 D1 6 5 D5 D4 17 18 16 15 14 13 12 11 10 OPEN 9 8 7 D7 D6
VRT
GND (ANALOG)
FIGURE 10. WHEN CLAMP IS USED (SELF-BIAS NOT USED)
12
HI2302 Application Circuits
(Continued)
+5V (DIGITAL) ACO4 0.1 CLOCK IN 16 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 D7 D6 D5 D4 D3 D2 D1 D0
VRT
+ 0.01 +5V (ANALOG) 19 18
-
17
VIDEO IN 33
20 21 0.1 10p 23 0.01 + 24 22
-
VRB
GND (ANALOG)
GND (DIGITAL)
FIGURE 11. SINGLE +5V POWER SUPPLY WHEN CLAMP IS NOT USED (SELF-BIAS NOT USED)
+3.3V (DIGITAL) ACO4 CLOCK IN OPEN CLAMP PULSE IN 0.01 +5V (ANALOG) 17 18 19 VIDEO IN 20 10 + 10p 0.1 33 21 22 23 24 +5V (ANALOG) 0.01 VREF 20K 25 26 27 28 0.01 GND DIGITAL 29 30 31 32 4 3 2 1 D3 D2 D1 D0 16 15 14 13 12 11 10 9 8 7 6 5 D7 D6 D5 D4 0.1
GND (ANALOG)
FIGURE 12. DUAL +5V/+3.3V POWER SUPPLY WHEN CLAMP IS USED (SELF-BIAS USED)
13
HI2302 Typical Performance Curves
fC = 50 MSPS SUPPLY VOLTAGE (mA) SUPPLY CURRENT (mA) 26 NTSC RAMP WAVE INPUT AVDD = DVDD = 5V 27 fC = 50 MSPS NTSC RAMP WAVE INPUT AVDD = DVDD TA = 25oC 25
25
24
23
-20
0
25
50
75
4.75
5 SUPPLY VOLTAGE (V)
5.25
AMBIENT TEMPERATURE (oC)
FIGURE 13. AMBIENT TEMPERATURE vs SUPPLY CURRENT
FIGURE 14. SUPPLY VOLTAGE vs SUPPLY CURRENT
SUPPLY CURRENT (mA)
25
SUPPLY CURRENT (mA)
35
fC = 50 MSPS SINE WAVE 1.9VP-P AVDD = DVDD = 5V TA = 25oC
20
30
15
NTSC RAMP WAVE INPUT AVDD = DVDD = 5V TA = 25oC
25
10
20
30
40
50
0.01
0.1
1
10
25
SAMPLING FREQUENCY (MSPS)
INPUT FREQUENCY (MHz)
FIGURE 15. SAMPLING FREQUENCY vs SUPPLY CURRENT
FIGURE 16. INPUT FREQUENCY vs SUPPLY CURRENT
MAXIMUM OPERATING RATE (MSPS)
fC = 50 MSPS 70 fIN = 1kHz, TRIANGULAR WAVE INPUT AVDD = DVDD = 5V
MAXIMUM OPERATING RATE (MSPS)
67
fC = 50 MSPS NTSC RAMP WAVE INPUT AVDD = DVDD
65
65
60
63
-20
0
25
50
75
4.75
5 SUPPLY VOLTAGE (V)
5.25
AMBIENT TEMPERATURE (oC)
FIGURE 17. AMBIENT TEMPERATURE vs MAXIMUM OPERATING FREQUENCY
FIGURE 18. SUPPLY VOLTAGE vs MAXIMUM OPERATING FREQUENCY
14
HI2302 Typical Performance Curves
fC = 50 MSPS SAMPLING DELAY (ns) 1 AVDD = DVDD = 5V OUTPUT LEVEL (dB) 0
(Continued)
-1
0
-1
fC = 50 MSPS -3 SINE WAVE 1VP-P INPUT AVDD = DVDD = 5V TA = 25oC
-20
0
25
50
75
0.1
1
10
100
AMBIENT TEMPERATURE (oC)
ANALOG INPUT FREQUENCY (MHz)
FIGURE 19. AMBIENT TEMPERATURE vs SAMPLING DELAY
FIGURE 20. FULL SCALE INPUT BANDWIDTH
60 50 fC = 50 MSPS AVDD = DVDD = 5V VIN = 2VP-P TA = 25oC fC = 50 MSPS AVDD = DVDD = 5V VIN = 2VP-P TA = 25oC
8 50 SFDR (dB) 7 ENOB
SNR (dB)
40 6
40
30
5 30
0.01
0.1
1
10
0.01
0.1
1
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FIGURE 21. ANALOG INPUT FREQUENCY vs SNR, EFFECTIVE NUMBER OF BITS (ENOB)
FIGURE 22. ANALOG INPUT FREQUENCY vs SFDR
fC = 10 MSPS AVDD = DVDD = 5V OUTPUT DATA DELAY (ns) OUTPUT DATA DELAY (ns) 12 CL = 15pF 12 tPLH 10
fC = 10 MSPS AVDD = 5V DVDD = 3.3V CL = 15pF
10
tPLH
8 tPHL 6 -20 0 25 50 75
8 tPHL 6 -20 0 25 50 75
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (oC)
FIGURE 23. AMBIENT TEMPERATURE vs OUTPUT DATA DELAY
FIGURE 24. AMBIENT TEMPERATURE vs OUTPUT DATA DELAY
15
HI2302 Typical Performance Curves
(Continued)
OUTPUT DATA DELAY (ns)
12
TA = 25oC tPLH
OUTPUT DATA DELAY (ns)
fC = 10 MSPS AVDD = DVDD = 5V
14 fC = 10 MSPS AVDD = 5V DVDD = 3.3V TA = 25oC tPLH
12
10 tPHL 8
10
8 tPHL 6
6 0 5 10 15 20 25
0
5
10
15
20
25
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 25. LOAD CAPACITANCE vs OUTPUT DATA DELAY
FIGURE 26. LOAD CAPACITANCE vs OUTPUT DATA DELAY
OUTPUT DATA DELAY (ns)
12 tPLH 10
fC = 10 MSPS AVDD = 5V CL = pF TA = 25oC
8 tPHL 6 3 3.5 4.5 5 5.5
DVDD SUPPLY VOLTAGE (V)
FIGURE 27. DVDD SUPPLY VOLTAGE vs OUTPUT DATA DELAY
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 16

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